The present invention relates generally to digital over-sampling filters that are clocked externally through the use of serial interfaces, such as the SPI interface (i.e., serial port interface). For example, the invention relates to systems including a 3-wire serial interface coupled to a recursive digital filter, and more particularly to avoiding instability of the recursive digital filter caused by input clock and data synchronization errors.
A 3-wire standard serial interface provides a simple way of submitting data to digital devices using 3 wires. FIG. 1 is a block diagram of a system 1 including a conventional 3-wire standard serial interface 2 coupled to a conventional recursive digital filter 3 that includes an external reset terminal 4. 3-wire standard serial interface 2 receives a serial data input signal SDIN, a corresponding serial clock signal SCLK, and a synchronization signal FSYNC, and in response produces a corresponding data signal PARALLEL DATA in parallel format as an input to recursive digital filter 3, and also reproduces the SCLK and FSYNC signals as inputs to recursive digital filter 3. In response, recursive digital filter 3 produces a filtered output signal OVERSAMPLED DATA in parallel format. Subsequently described FIG. 2A is a more detailed diagram of the 3-wire standard serial interface of FIG. 1, and subsequently described FIG. 3A is a more detailed diagram of a conventional recursive digital filter.
Numerical stability is critical in digital filter design, and all digital filters are designed to be stable. Finite Impulse Response (FIR) filters are inherently stable since they do not contain poles. Infinite Impulse Response (FIR) filters are stable as long as their poles lie outside the unit circle. Without stability, useful filtering action can not occur because the output of the digital filter contains unwanted oscillations which can have very high amplitudes that result in arithmetic over-flows.
Certain FIR filters are implemented recursively, similar to FIR filters. Such recursive implementations greatly simplify the hardware requirements for FIR filters. Examples of such FIR filters are over-sampling SYNC filters (i.e., COMB filters). Also, the filter stability assumes that the fundamental equation which defines the digital filter is maintained and satisfied at all times. However, various digital faults can occur in an ordinary printed circuit board environment wherein a digital over-sampling filter is controlled via a serial interface. These faults can include bit errors or synchronization errors due to ground bounce, electrical over-stresses such as those caused by electro-static discharge (ESD) events, or a “bug” in microprocessor software. Since such faults can occur with appreciable probability in some applications, it would be desirable to provide fault tolerant digital filtering, since it may be critical that the digital filter not go into a persistent unstable state after a fault condition.
There are various high-speed DAC (digital to analog converter) applications wherein a high-speed serial interface is beneficial to a parallel interface. One typical application is to provide a DAC with a parallel interface so that all bits of a digital input word are written to the DAC simultaneously. A high-speed “S” clock is used for oversampling. However, providing a DAC with the standard 3-wire SPI port and using the S clock for oversampling is not common, since most high-speed DACs have a parallel interface. But in a few applications it has been found to be advantageous to provide a high-speed DAC with a serial interface to save printed circuit board space. One application for this technique is in digital converter applications for TV systems. Some TV set manufacturers now specify use of a high-speed DAC with a serial interface rather than a parallel interface. For example, in the digital convergence unit (DCU) of some projection TV systems, six separate 16-bit DACs with serial interfaces are used to position the RGB signals correctly on the TV projection screen using available products such as the present assignee's PCM56, PCM55 or Pioneer's CD0031AM. In these digital convergence units, waveforms of up to 31.75 KHz in fundamental frequency are generated, and analog filters then are used smooth the waveforms.
A simple improvement to reduce the cost and performance requirements of the foregoing analog filters is to include a digital over-sampling filter within the DACs of the digital convergence unit. This reduces the TV manufacturer's costs associated with the analog filter. However, there are two main requirements for introducing a digital over-sampling filter into the existing TV systems. First, there is a need for the interface to be compatible with the existing 3-wire serial interface schemes (i.e., for backward compatibility with PCM56-like interfaces), and second, there is a need for ensuring stability of the digital over-sampling filter at all times, including during and after fault conditions caused by unexpected phenomena such as lightning or ESD events. If there is any kind of error or fault condition in data and/or clock synchronization, the digital filter may become unstable, and in a recursive digital filter the unstable condition ordinarily persists until the user or a microcontroller resets it. Having to reset the recursive digital filter may be very inconvenient.
FIG. 2A which shows a very basic conventional 3-wire serial interface circuit 50, which for simplicity is illustrated as an 8-bit interface (although a 16-bit serial interface circuit has been used in an actual implementation of the present invention). 8-bit, 3-wire serial interface circuit 50 includes a row of 8 D-type flip-flops 51-1,2 . . . 8 and a row of 8 D-type flip-flops 52-1, 2 . . . 8. The serial data signal SDIN is connected to the D input of the next of flip-flop 51-1, and its output Q is connected to the D input of flip-flop 51-2, and so on such that the output of each of flip-flops 51-2 through 51-7 is connected to the input of the next flip-flop. A serial clock signal SCLK is connected to the clock input of each of flip-flops 51-1,2 . . . 8. The output of flip-flop 51-1 is connected to the D input of flip-flop 52-1, the output of flip-flop 51-2 is connected to the D input of the next flip-flop 52-2, and so on until the output of flip-flop 51-8 is connected to the D input of flip-flop 52-8. The clock inputs of flip-flops 52-1,2 . . . 8 are connected to the output of an inverter 53 which has the frame synchronization signal FSYNC connected to its input. The outputs of flip-flops 52-1,2 . . . 8 produce a parallel 8-bit digital word D0,D1 . . . D7.
The timing diagram in FIG. 2B shows the relationship between a particular serial data word SDIN, serial clock signal SCLK and frame sync signal FSYNC, and indicates the interval of each byte of valid output data D0-D7.
In operation, the lower row of flip-flops 52-1,2 . . . 8 in effect mirrors the contents of the upper row of flip-flops 51-1,2 . . . 8, and FSYNC enables the contents of flip-flops 51-1,2 . . . 8 onto the output conductors conducting the 8-bit digital output word D0-D7.
But the digital output word D0-D7 produced by 3-wire serial interface 50 will be erroneous if, for example, there is an extra SCLK cycle. Also, if a FSYNC pulse does not arrive on time, the output D0-D7 will be erroneous. If incorrect serial data SDIN is written into 3-wire serial interface 2 as a result of an input synchronization error, the output D0-D7 will be incorrect, but as soon after correct data has been written, 3-wire serial interface 2 again begins to produce the correct parallel data output D0-D7.
If the foregoing incorrect digital output word D0-D7 is coupled to the input of recursive digital filter 3, the result is persistent, uncorrectable instability in recursive digital filter 3 which cannot be eliminated any way other than by resetting it and then entering correct serial SDIN data, and SCLK and FSYNC signals into 3-wire standard serial interface 2.
The following explanation of recursive digital filters hopefully will provide a basis for better understanding of the present invention. Recursive digital filter 3 of FIG. 1 can be a SYNC3 filter. A SYNC filter is one that performs a sine(x)/x filtering of the filter input x(n). Three SYNC filters coupled in cascade are known as a SYNC3 filter, which is said to perform a SYNC3 function or to have a “SYNC3 response”. Referring to FIG. 3A, a practical hardware recursive implementation of a digital SYNC3 filter 3 of FIG. 1 is shown. As subsequently explained, digital filter 3 is actually implemented as a SYNC2 filter which, in combination with 3-wire standard serial interface 2, performs a SYNC3 function. Recursive digital filter 3 has a zero order hold input signal x1(n) applied to a “delay by N” element 55, which delays x1(n) by N SCLK periods. A “zero order hold” function consists simply of repeating the present input data x(n) N times. (The SYNC2 filter and the SYNC3 filters referred to can be considered to be specific examples of generalized SYNCN and SYNC(N+1) filters, respectively, where N can be an integer greater than 2.)
Zero order hold input signal x1(n) also is applied to the (+) input of a subtractor 56. The output of delay element 55 is subjected to an arithmetic shift left (ASL) function by an arithmetic shifter 57 and the result is applied to a (−) input of subtractor 56. The output of subtractor 56 is applied to one input of an adder 59. The output of delay element 55 also is input to a delay by N element 58, the output of which is coupled to another input of adder 59. The output of adder 59 is subjected to 8 bit arithmetic shift right (ASR) operation by arithmetic shifter 60. Its output is coupled to the (+) of a subtractor 61, the output of which is applied to one input of an adder 62. The output of adder 62 is coupled to the output of digital filter 3 at which the filter output y[n] is produced. y[n] is fed back and subjected to a 1 SCLK period delay by delay element 66, the output of which is subjected to a one bit arithmetic shift left operation by arithmetic shifter 65, the output of which is coupled to the other input of adder 62. The output of delay element 66 is also subjected to a 1 SCLK delay by another delay element 64, the output of which is coupled to the (−) input of subtractor 61.
The hardware implementation of a conventional SYNC3 recursive digital filter 3 as shown in FIG. 3A can be connected to a standard 3-wire serial interface as shown in FIG. 1, wherein the SDIN (serial data input) input terminal carries the serial input data and the SCLK (serial clock) terminal serves as the continuous over-sampling clock input, and the FSYNC (frame synchronization) terminal serves as an input wherein 16-bit input data is latched at each time frame. The SYNC3 digital filtering function performed by the combination of 3-wire standard serial interface 2 and recursive digital filter 3 as shown in FIG. 3A is defined by equation:
                              H          ⁡                      (            z            )                          =                                            (                                                1                  N                                ⁢                                                      1                    -                                          z                                              -                        N                                                                                                  1                    -                                          z                                              -                        1                                                                                                        )                        3                    .                                    Eq        .                                  ⁢                  (          1          )                    
The basic recursive hardware representation of the SYNC3 filter 3 is represented by the diagram of FIG. 3B, which is a time domain representation including an input x(n) applied to a first SYNC filter 23, the zero order hold output x1(n) of which is applied to the input of a second SYNC filter 24. The output of SYNC filter 24 is applied to the input of a third SYNC filter 25. The output of the third SYNC filter 25 is the SYNC3 filtered output y[n]. This hardware implementation utilizes a zero order hold (stored in a serial-to-parallel conversion register), represented by x1(n). The filtered output y[n] is given by the following recursion formula:
                                          y            ⁡                          [              n              ]                                =                                                    1                                  N                  2                                            ⁢                              (                                                      x                    ⁡                                          [                      n                      ]                                                        -                                      2                    ⁢                                          x                      ⁡                                              [                                                  n                          -                          N                                                ]                                                                              +                                      x                    ⁡                                          [                                              n                        -                                                  2                          ⁢                          N                                                                    ]                                                                      )                                      +                          2              ⁢                              y                ⁡                                  [                                      n                    -                    1                                    ]                                                      -                          y              ⁡                              [                                  n                  -                  2                                ]                                                    ,                            Eq        .                                  ⁢                  (          2          )                    where, ‘n’ is the time index that corresponds to oversampling serial clock signal SCLK, ‘N’ is the over-sampling ratio and therefore represents the time index that corresponds to frame synchronization signal FSYNC, and y[n] is the filter output signal OVER-SAMPLED DATA.
Equation (2) shows that SYNC3 filter 3 can be realized by 2 adders, 2 subtractors, and arithmetic shifters. No multipliers are required. (A non-recursive implementation of the same FIR SYNC3 filter 3 requires a convolution operation with 46 filter taps. However, the non-recursive implementation is rarely used, and it is common industry practice to use a recursive implementation of this filter.)
The recursive filter 3 implementations shown in FIGS. 3A and 3B are stable as long as filter Equation (3) is valid.
The SYNC3 implementation shown in FIG. 3B has a third order transfer function in the Z domain. In the time domain representation of FIG. 3B, it is a cascade of three SYNC filters each having the same frequency response. The easiest way to understand what that means in the time domain is to refer to the three time-based diagrams A, B and C in FIG. 3C. In diagram A, it is assumed that the input x(n) to this SYNC filter 23 includes 3 digital input words, represented by the vertical lines at FSYNC cycles 1, 2 and 3, respectively, wherein every time FSYNC goes low there is another digital input word represented by another such vertical line. The heights of the three vertical lines represent values of the three digital words. The oversampling ratio N is 4 in this simplified example. In diagram B of FIG. 3C the time base is a SCLK time frame rather than the FSYNC time frame for diagram A. In this simplified example, there are 4 SCLK cycles in each FSYNC cycle, although in a practical design there might be 16. The input data x(n) is the same for diagram B as for diagram A, so the corresponding vertical lines for diagram B are the same as for diagram A. Diagram B actually shows the sampled input waveform in the SCLK time domain.
Diagram C of FIG. 2B illustrates a zero order hold function x1(n) that provides 4 SCLK cycles or periods per FSYNC time frame period, which in effect “pads” the input data x(n) with itself to produce the zero order hold signal x1(n).
A convenient property of a SYNC filter is that its components can produce a zero-order hold function. So the data input signal x(n) is passed through a first SYNC filter, for example SYNC filter 23 in FIG. 3B, and the zero order hold result x1(n) is the oversampled input data illustrated in diagram C, wherein the zero order hold signal x1(n) signal is simply the result of repeating the input present data x(n) in 3-wire standard serial interface 2 until the next new data word arrives. This accomplishes the desired oversampling by N. Since the input data x(n) is already being held in 3-wire standard serial interface 2, is not necessary to provide SYNC filter 23 of FIG. 3B to provide the foregoing zero order hold function. Therefore, the input data is valid during every serial clock SCLK time frame until the next parallel input data word arrives. Therefore, to obtain a SYNC3 filter, only SYNC filters 24 and 25 in FIG. 3B actually need to be implemented. SYNC filters 24 and 25 together have a SYNC2 transfer function in the Z domain represented by the expression[1/N*(1−Z−N)/(1−Z−1)]2,which is the transfer function of the filter as shown in FIG. 3A. When this equation is expanded in the time domain, the result is previous Equation (2), which can be implemented by means of two adders and two subtractors and some delay elements.
The division by N2 in Equation (2) is accomplished by an arithmetic right-shift, and the multiplications by 2 are accomplished by arithmetic left shifts. The indices −1 and −2 represent a delay of 1 SCLK period. The index N corresponds to a delay of N SCLK periods. An index of 2N corresponds to a delay of 2N SCLK periods. Therefore, an index N corresponds to a delay by a FSYNC period, an index of 2N represents a delay of 2 FSYNC periods, an index 2 represents a delay of 2 SCLK periods, and an index 1 represents a delay of 1 SCLK periods. The lower case “n” indexes are time indexes. The “n” indexes correspond to the SCLK periods, so if n changes, that means a new SCLK cycle has arrived.
FIG. 4 is a waveform produced by normal digital filtering by system 1 of Prior Art FIG. 1, wherein recursive digital filter 3 is a 16× over-sampling SYNC3 filter operating to smooth to a digital sine wave designated by “A”. (The glitches are simulation artifacts of the simulation system by Spectre/Verilog co-simulation.) The resulting filtered output signal OVER-SAMPLED DATA designated by “B”. Recursive digital filter 3 works properly as long as there are 16 SCLK cycles per each FSYNC, which is the assumed “zero faults” condition assumed for the simulated results shown in FIG. 4. The filtered output waveform “B” is a smoothed version of the digital input waveform “A” applied to recursive digital filter 3 by 3-wire standard serial interface 2 and, as indicated by A1,B1, closely follows digital input waveform “A” without causing recursive digital filter 3 to become unstable. Note that the instability in the filter actually is strongly “understated” by the simulated waveform B in FIG. 5.
Once the above-mentioned recursive filter equation for y[n] is invalidated, nothing can be done to fix the problem except to reset the recursive filter. Therefore, a feature of most recursive filter designs is an external reset switch that can be externally actuated, for example to cause a microcontroller to reset the filter if its output becomes meaningless.
FIG. 5 is a simulated waveform which illustrates the persistent instability that occurs in recursive digital filter 3 in response to an undesired 17th SCLK pulse. The simulated curves in FIG. 5 assume that the undesired 17th SCLK pulse, which is in effect an unwanted pulse superimposed (e.g., in response to an ESD event) on the normal SCLK sequence at about 10 microseconds along the horizontal time axis as indicated by vertical line “C”. This causes an unexpected pulse “A1” in the digital sine wave “A” which represents the serial data SDIN, and also causes an abnormal feature “B1” in the simulated filter output waveform B, and also causes arithmetic overflow in filter 3 which results in the abnormal features “B2” and “B4” in the simulated filter output waveform “B”.
The instability of digital filter 3 persists even though the input glitch (in the form of the undesired 17th SCLK pulse) occurs only once. This is because of the recursive implementation of the recursive digital filter 3.
Referring to FIG. 5, in each step of the digital sine wave “A” input to recursive filter 2 there are 16 SCLK pulses. The vertical line at the 10 μs point of the horizontal axis indicates where an unwanted SCLK pulse is “inserted” in the simulation process. The additional SCLK pulse at time C only affects one cycle of 3-wire standard serial interface 2, and that is indicated by A1 in FIG. 5. This is because 3-wire standard serial interface 2 recovers as soon as its inputs SCLK and FSYNC become correctly synchronized with SDIN, and soon thereafter the data through serial interface 3 is output correctly, as can be seen from the subsequent portion of the A waveform shown in FIG. 5. However, once the undesired 17th SCLK pulse occurs, it causes the above mentioned equation of recursive filter 3 to be violated, and therefore digital filter 3 becomes unstable and remains that way until it is reset. Feature B5 in FIG. 5, indicates that there is a divergence where waveform B no longer follows the digital input waveform A. It should be noted that in a physical implementation of filter 3, the divergence B5 actually is much more pronounced or exaggerated and appears simply as “garbage”.
FIG. 6 is a simulated waveform which illustrates persistent instability that is produced in recursive digital filter 3 in response to an undesired FSYNC pulse. The simulated curves in FIG. 6 assume that the undesired FSYNC pulse, which is in effect an unwanted pulse superimposed on the normal FSYNC sequence (e.g., in response to an ESD event) at about 10 microseconds along the horizontal time axis as indicated by vertical line “C”. This causes an abnormal feature “B1” in simulated filter output waveform B, and also causes the abnormal feature “B2” in the filtered output waveform “B” due to arithmetic overflow in recursive digital filter 3. This occurs even if the input data PARALLEL DATA is never read incorrectly by digital filter 3.
The instability of recursive digital filter 3 persists even though the input glitch in the form of the undesired FSYNC pulse occurs only once. The “glitch instant” is at 10 μs, and waveform A in FIG. 6 shows that the extra FSYNC glitch or pulse does not cause any error in the digital input waveform A. This is because the serial interface re-loads the current input data after the extra FSYNC pulse is inserted, so the present parallel data input to recursive filter 3 does not change. 3-wire standard serial interface 2 is not “aware” of any problem with the FSYNC signal. However, this again invalidates the filter equation, so recursive filter 3 becomes unstable, resulting in abnormal features B1, B2 and B3 in waveform B FIG. 6 and persistent instability of recursive filter 3, until it is reset.
The prior art approach to the problem of recursive filter instability is to assume that the SCLK and FSYNC pulses are always correctly synchronized with respect to the serial data SDIN, and this ordinarily is a reasonable assumption. However, in applications in which this is not a reasonable assumption it may be very inconvenient to require the user or a microcontroller to recognize the problem and reset the recursive digital filter.
Thus, there is an unmet need for an improved system including a 3-wire interface and a recursive digital filter and method that avoid persistent digital filter instability as a result of data/clock errors.
There also is an unmet need for an improved system including a 3-wire interface and a recursive digital filter and method which avoids the difficulties of the user having to actuate an external reset control of the recursive digital filter to halt persistent digital filter instability that otherwise occurs as a result of data/clock errors.
There also is an unmet need for a recursive digital filtering system including a 3-wire serial interface wherein fault-free input signals cannot be reasonably assumed.